From 72a928a840fcfada2de9da80f917c693cbcde575 Mon Sep 17 00:00:00 2001 From: Mylloon Date: Fri, 9 Dec 2022 16:58:17 +0100 Subject: [PATCH] fix registers --- baselib.ml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/baselib.ml b/baselib.ml index 3983e7f..63a650e 100644 --- a/baselib.ml +++ b/baselib.ml @@ -16,10 +16,9 @@ let builtins = List.fold_left (fun env (fn, impl) -> Env.add fn impl env) Env.empty - [ "%add", [ Lw (T0, Mem (SP, 0)); Lw (T1, Mem (SP, 4)); Add (V0, T0, T1) ] - ; "%sub", [ Lw (T0, Mem (SP, 0)); Lw (T1, Mem (SP, 4)); Sub (V0, T0, T1) ] - ; "%mul", [ Lw (T0, Mem (SP, 0)); Lw (T1, Mem (SP, 4)); Mul (V0, T0, T1) ] - ; "%div", [ Lw (T0, Mem (SP, 0)); Lw (T1, Mem (SP, 4)); Div (V0, T1, T0) ] - (* %div: reversal of T1 and T0 ?? *) + [ "%add", [ Lw (T0, Mem (SP, 4)); Lw (T1, Mem (SP, 0)); Add (V0, T0, T1) ] + ; "%sub", [ Lw (T0, Mem (SP, 4)); Lw (T1, Mem (SP, 0)); Sub (V0, T0, T1) ] + ; "%mul", [ Lw (T0, Mem (SP, 4)); Lw (T1, Mem (SP, 0)); Mul (V0, T0, T1) ] + ; "%div", [ Lw (T0, Mem (SP, 4)); Lw (T1, Mem (SP, 0)); Div (V0, T0, T1) ] ] ;;